Conventionally, integrated circuit (IC) designers use adaptive voltage scaling (AVS) as a technique to minimize power usage in their designs. In these approaches, the IC is monitored for performance parameters, and if the performance parameters are met, the voltage is lowered iteratively until reaching a lower bound. However, in use, ICs that are designed with AVS can be more susceptible to heat-based failure when their voltage is raised. Additionally, the localized front-end-of-the-line (FEOL) structures used to monitor temperature and voltage levels in these AVS ICs can provide inaccurate measurement and estimation of temperatures and voltage levels in the larger circuit. Even further, the measurement inaccuracies in these AVS ICs can require a guard band, which can increase design and fabrication complexity and costs.